Semiconductor devices manufacture

ABSTRACT

SEMICONDUCTOR STRUCTURES HAVING MULTI-LAYER METAL CONDUCTORS FORMED ON THE SURFACE OF THE SEMICONDUCTOR DEVICES AND HAVING EXCESS METAL BETWEEN THE CONDUCTORS REMOVED BY SPUTTER ETCHING IN AN ATMOSPHERE WHICH PRODUCES OXIDATION OF ONE OF THE METAL LAYERS OF SAID CONDUCTORS. THE METAL COMPOUND MASK THUS FORMED INHIBITS THE ETCHING PROCESS IN THE REGIONS WHERE THE OIDIZED LAYER IS EXPOSED AND PROTECTS THE ACTIVE COMPONENTS BENEATH THE LAYER. THE OXIDIZED PORTIONS OF THE MASKING LAYER ARE THEN REMOVED BY A SUITABLE SOLVENT OR ETCH. A CHEMICAL ETCHING METAL COMPOUND MASK MAY BE FORMED OF A METAL AND THE SEMICONDUCTOR MATERIAL FOR SEPARATING THE CHIPS FROM THE WAFER BY ANISOTROPIC ETCHING.

5Pi- 17, 1974 K. H. TIEFERT 3,836,446

I SEMICONDUCTOH DEVICES MANUACTURE @riginal Filed May lO. 1971 2SheetS-Sheetl Sept. 17, 1974 K. H. Tier-'ERT 3,836,445

SEMI CONDUCTOR vDEVIIIES MANUFACTURE Original Filed May'lO. 1971 2Sheets-Sheet 2 3,836,446 SEMICONDUCTOR DEVICES MANUFACTURE Karl H.Tiefert, Los Altos, Calif., assignor to Raytheon Company, Lexington,Mass.

Original application May 10, 1971, Ser. No. 141,857, now abandoned.Divided and this application Sept. 20, 1972, Ser. No. 290,593

Int. Cl. C23b 5/50; (123e 13/02, 15/.00 U.S. Cl. 204-192 19 ClaimsABSTRACT OF THE DISCLOSURE Semiconductor structures having multi-layermetal conductors formed on the surface of the semiconductor devices andhaving excess metal between the conductors removed by sputter etching inan atmosphere which produces oxidization of one of the metal layers ofsaid conductors. The metal compound mask thus formed inhibits theetching process in the regions where the oxidized layer is exposed andprotects the active components beneath the layer. The oxidized portionsof the masking layer are then removed by a suitable solvent or etch. Achemical etching metal compound mask may be formed of a metal and thesemiconductor material for separating the chips from the wafer byanisotropic etching.

This is a division of application Ser. No. 141,857, filed May l0, l97l,now abandoned.

BACKGROUND OF THE INVENTION Semiconductor integrated circuit deviceshave been formed with connecting leads deposited on the active elcmentside of a semiconductor chip by vapor deposition using a metal, such asaluminum, with the undesired portions being oxidized through a mask andremoved by etching. Such structures have undesirable operatingcharacteristics since the aluminum may interact, for example whensubjected to high current surges, with the active semiconductor elementsproducing ion migration or other deleterious defects.

Multiple layer metal lead systems have been used in which layers oftitanium and platinum are deposited on a semiconductor region and thelayers were selectively removed by etching through a photoresist mask.This process etches some metal underneath the mask and reduces theprecision of location and extent of the etched regions. In addition,since the different layers of metals requires different etches, a seriesof etching steps is required thereby increasing the production costs.

SUMMARY OF THE INVENTION This invention provides for controlling theetching of semiconductor devices with a mask formed of a metal compound.The mask may be, for example formed by forming an apertured layer of alight metal such as titanium on the surface to be etched, and sputteretching the surface in an atmosphere having a constituent which reactswith the metal to produce a layer which sputter etches more slowly thanthe material which is exposed through the apertures and which is to beremoved by etching. Since sputter etching does not substantiallyundercut an etching mask highly precise location and shape of etchedregions can be achieved. This precision can be further enhanced by usingthe metal compound mask of this invention for sputter etching sincesputter etching will somewhat enlarge the apertures in a photoresistmask, but will not substantially enlarge the apertures in the metalcompound which is continuously formed during the etching process.

This invention further discloses that the mask may be formed of a metalwhich makes up a portion of the semi- United States VPatent IO iceconductor leads and may be used as a stopping layer for a sputter etchin regions between the leads, so that several layers of differentmaterials may be removed by a single sputter etching step and thesputter etching process will stop automatically when the stopping layeris reached. This is achieved by coating the surface of a semi-conductorchip containing active elements, whose surface regions have beenpassivated by a passivation layer having openings at the contact pointsto said elements, with a iirst layer of masking metal such as titanium,a second layer of barrier metal such as platinum, which preventspenetration of undesired metal into the semiconductor material, and athird layer of metal, such as gold, which is preferably the same metalas that used in the leads. The lead regions are then demarked on thegold layer by a conventional photoresist mask through which the leadsare plated to a thickness substantially greater than the combinedthickness of the three lower layers.

The excess lead material between the lead members as Well as the barrierlayer material can then be removed by removing the photoresist mask andsputter etching the surface in an oxidizing atmosphere at reducedpressure which removes only a small portion of the surface of the platedleads, but removes all of the lead metal layers and barrier metal layerbetween the leads. However, due to the oxidizing atmosphere the maskinglayer is oxidized and prevents further sputter etching so that theentire wafer may have all of the regions between the leads freed of leadlayer metal and barrier layer metal without removing sufficient maskinglayer metal to damage the passivation layer and active semiconductorregions. The exposed masking layer metal is then removed by a chemicaletch.

This invention further discloses that integrated semiconductor circuitsmay be readily formed with interconnections of different elements of thecircuit through multilayer conductors which cross over, and areinsulated from, each other. Sputter etching in an atmosphere which formsa metal compound with at least one of the metal layers is used to removeexcess metal between the interconnectors.

This invention further discloses that a metal compound mask may be usedto separate the chip from the semiconductor wafer after the activesemiconductor elements have been formed.

More specifically, the side of a silicon wafer, opposite to the sidecontaining the active elements, is coated with a metal such as platinum,and a photoresist mask having apertures formed therein Where the chip isto be separated from the wafer. The platinum in the apertures of themask is removed by chemical etching, the photoresist mask is removed bya solvent, the platinum layer thermally converted to platinum silicide,and the wafer subjected to chemical etching through the apertures in theplatinum silicide. If the wafer surfaces are perpendicular to thecrystallographic axis, an etch such as sodium hydroxide may be usedwhich will etch through the wafer faster than it will etch along thewafer surface, thereby providing an anisotropic, or preferential etch.Indicating nomenclature may, if desired, be also formed in the platinumsilicide layer which is retained on the finished chip.

DESCRIPTION OF THE DRAWINGS FIG. l illustrates a cross-sectional view ofa semiconductor body having active semiconductor elements formedtherein;

FIG. 2 illustrates the body of FIG. 1 with additional coatings of metalinterconnecting layers between the elements;

FIG. 3 illustrates a semiconductor body of FIG. 2 with the leads formedthereon;

FIG. 4 illustrates the body of FIG. 3 with the metal formed between theleads and desired interconnecting regions removed by sputter etching;

FIG. 5 illustrates the semiconductor body separated into portions bypreferential etching;

FIG. 6 illustrates one of the portions of the body of FIG. 5 attached toa substrate having interconnecting leads;

FIG. 7 illustrates a further embodiment of the invention in which afirst layer of interconnecting conductors is formed on a semiconductorbody; and

FIG. 8 illustrates an embodiment of the invention wherein a second layerof interconnecting conductors is formed over the rst layer of conductorsand insulated therefrom.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, thereis shown a portion of a semiconductor wafer 10 having a plurality ofactive semiconductor elements 11 formed in an epitaxial layer on onesurface of the wafer. As illustrated herein, the active semiconductorelements are a diode and a transistor; however, any desired activeand/or passive combination of semiconductor elements could be formed onthe surface of the wafer 10 in accordance with well known practice.While any desired crystallographic orientation may be chosen for thewafer 10, it is preferred that the [100] crystallographic plane beoriented parallel to the epitaxial layer.

The surface containing the epitaxal layer is preferably passivated inaccordance with well known practice after the diffusion steps are donethrough a silicon dioxide mask, for example, by forming a layer ofsilicon nitride on the surface of the silicon dioxide to provide acombined surface dielectric layer 15. Apertures are formed in the layer15 in accordance with well-known practice by means of a photoresist maskand etching process in the regions where it is desired to make contactwith the semiconductor elements. The contact regions are coated withplatinum and heated to produce a surface layer of platinum silicide (notshown).

Referring now to FIG. 2 there is shown the body illustrated in FIG. 1 inwhich a three layer metal coating has been formed on the passivatedsurface with portions of the metal extending through the openings in thepassivated layer and contacting the active semiconductor elements. Thesurface is rst coated with a uniform layer of a light metal 16 such astitanium, having a thickness of, for example, l000 to 2000 angstroms byvacuum deposition or sputtering. While other materials may be used, ithas been found that titanium produces a good bond with semiconductormaterial and hence produces reliable devices. The surface is then coatedby vacuum deposition or sputtering with a barrier layer 17 of metal,such as platinum, having a thickness of, for example, 3000 angstroms.This provides isolation between the semiconductor material and theconductive lead metal, such as gold which might otherwise penetrate intothe semiconductor region during elevated temperature periods. Thesurface is then coated with a layer 1S of lead metal such as gold whichmay be, for example, 2000 angstroms thick on which the leads are to beformed by electrodeposition.

Referring now to FIG. 3, the three layers 16, 17 and 18 are covered witha photoresist mask 19 having openings therein to expose regions of thesurface of the layer 18 where the heavy metallic leads are to be formed.Preferably, a layer 2S of metal such as titanium is formed by vacuumdeposition or sputtering between the gold layer 18 and the photoresistmask 19. Layer may be, for example 500 angstroms thick, and the portionsexposed through the opening in mask 19 are removed by chemical etchingin a solution of, for example, 10 parts of a 40% solution of NH4OH and 1part of a 40% solution of HF. 75

The wafer is placed in an electrolytic bath and the gold leads are builtup as indicated at 20 to a depth of, forexample, .0001 byelectrodeposition. Titanium layer 25 aids in preventing excessivemushrooming of the plated region beyond the edges of the originalopenings formed in mask 19. Mask 19 is then removed by a solvent inaccordance with well-known practice and layer 25 is removed by etchingin a solution of H2O2 and NH4OH.

Referring now to FIG. 4 there is shown the wafer and plated leadstructure of FIG. 3. The wafer is sputter retched in an argon oxygenatmosphere which removes a small portion of the leads 20 and the layers18 and 17 until the titanium layer 16 is reached lwhich oxidizes to forma titanium dioxide layer 21.

The rate at which the titanium dioxide layer 21 is sputter etched in theargon atmosphere is very substantially slower than the rate at which anyof the other materials exposed to sputter etching process are removedand as such it may be regarded as a barrier.

The titanium dioxide layer 21 is subsequently removed by chemicaletching in a solution of H2804 and H2O2. Thus, it may be seen thatintegrated circuits formed in accordance with this invention may havethe active elements positioned more closely and more accurately than hasheretofore been possible and the production rate may be increasedwithout increase in rejection of faulty units by accidental etchingthrough to the active semiconductor elements.

The sputter etching rate varies with the etching current which may beadjusted to any desired density of the region to be etched and thevoltage between the electrode and the semiconductor may be adjusted atany desired level. It has been found that this sputter etching processmay be used to remove layers of materials such as gold, platinum,copper, silicon dioxide and silicon nitride up to 50,000 angstroms thickwhile masking adjacent areas with a thin titanium mask only 1000 to 2000angstroms thick since as the titanium dioxide formed on the surface ofthe titanium layer is removed by sputter etching additional titaniumdioxide is formed with the sublayer of titanium continuously.

It has also been found that the sputter etching, which is preferablycarried out with an RF voltage, produces some redepositing materialsputtered from other portions of the target electrode, of the dischargeback on to the work being sputter etched, and such back deposition canbe minimized by using a sputter etching target as a substrate holder forthe work, which target is made of a light metal such as titanium oraluminum. It is contemplated that this invention can be used in avariety of processes other than the removal of interconnecting metalbetween the leads of semiconductor integrated circuits. For example, itis particularly applicable in those processes where photoresist maskswould deteriorate such as processes carried out at elevatedtemperatures. In addition, the light metal dioxide mask Will not shrinkor change shape to any substantial extent while the photoresist maskwill change shape under a variety of conditions. It is also contemplatedthat any desired metal and gas constituent could be used which wouldreact during the sputtering process to form the masking component andthat the remainder of the atmosphere can be made up with any other gaswhich does not react and more specifically it is contemplated that anyof the noble gases can be employed. f

Referring now to FIG. 5, there is shown the Wafer 10 with theinterconnecting leads 20 formed to interconnect for the active elements11 and to connect the active elements with external circuitry. The Wafer10 is segregated into chips each containing several of theactive'elements 11 by removing suicient semiconductor material from theopposite surface of the wafer to obtain a wafer of a uniform thicknessof, for example, several mils, coating the back surface of the Waferwith a photoresist mask 22 forming platinum silicide in the unmaskedregions, removing the mask to expose the silicon wafer in the desiredseparation regions, and etching the separation regions with an etchingsolution, such as sodium hydroxide, which will have a preferentialetching characteristic. If the semiconductor is silicon having the [100]crystallographic plane parallel to the epitaxial layer, such apreferential etch will etch in a direction normal to the [100]crystallographic plane at a substantially greater rate than in adirection parallel thereto.

Referring now to FIG. 6, there is shown the semiconductor portion havingthe active elements 11 positioned face down on a supporting substrate 26which may be of plastic, ceramic or fiber board. A plurality ofinterconnecting leads 27 on substrate 26 have portions contacting theprojecting portions 24 of the leads 20 which are exposed for theapplication of a welding electrode by means of which the portions 24 arewelded to the conductors 27. It is contemplated that any other desiredbonding process such as soldering may be used. The space between thebody 10 and the substrate 25 in between the conductors 27 and the leads20 may be filled with any desired insulating material 28 such as epoxyresin to aid in the transfer of heat generated from the semiconductorchip to the substrate 25.

Referring now to FIG. 7, there is shown an embodiment of the inventionwherein multiple layer interconnection of components of elements can beachieved. A substrate having an epitaxial layer 30 thereon hascomponents 31 of any desired type formed in the layer and extending tothe surface of said layer. Components 31 may be of any desired type suchas transistors, diodes or resistors formed by diffusion techniques inaccordance with well known practice.

In the regions where the first interconnects are to be formed, aperturesare formed in a layer 32 formed on the surface of the epitaxial layer30. Layer 32 may be, for example, silicon dioxide passivated with alayer of silicon nitride. The apertures in layer 32 are formed bymasking the surface with a photoresist, exposing and developing thephotoresist and dissolving the developed regions where the apertures areto be formed in accordance with well- 'known practice. The portions oflayer 32 exposed through the apertures in the photoresist mask are thenremoved by etching, in accordance with well-known practice to expose thesilicon regions in the epitaxial layer 30 and the platinum silicidecontacts are formed as previously described.

Layers of titanium 35, platinum 36, gold 37 and titanium 38 are thenapplied by vapor deposition or sputtering. Titanium layer 35 may be, forexample, approximately 1000 angstroms thick, platinum layer 36approximately 3000 angstroms thick, gold layer 37 approximately 10,000angstroms thick and titanium layer 38 approximately 1500 angstromsthick.

Regions other than the regions above the apertures in layer 32 and theregions where cross connectors between elements are to be made by layers35, 36 and 37, are then demarked by being exposed through a photoresistmask 39 to a chemical etch to remove titanium layer 38. The etch is, forexample, l0 parts of a 40% solution of NH4OH and l part of a 40%solution of HF.

The photoresist layer is then removed by a conventional solvent and theportions of layers 36 and 37 not covered :by the layer 38 are thenremoved by sputter etching in an oxidizing atmosphere such as lowpressure argon and oxygen which removes these layers but oxidizes theexposed regions of titanium layers 35 and 38 to produce a titaniumcompound which sputter etches at a substantially lower rate than layers36 and 37 thereby masking such regions. The titanium also produces goodadherence with silicon and with other metals such as platinum layer 36which prevents diffusion of gold layer 38 into the silicon at elevatedprocessing and/or operating temperatures.

Sputter etching substantially reduces undercutting of adjacent maskedregions. It is contemplated that other 6 layers besides titanium couldbe used to provide the dual purpose of interconnecting the siliconelements with the metallic circuits and forming compounds with thesputter etching atmosphere which resist sputter etching to a greaterdegree than the metal elements.

The exposed portions of layer 35 and the remainder of layer 38 whichserved as a sputter etching mask are then removed by chemical etching,for example, by a solution of 7 parts of a 95% solution of H2SO4 and 3parts of a 30% solution of H2O2, so that the passivation layer 32 isexposed `between the leads made up of the remainder of layers 35, 36 and37.

FIG. 8 shows a final layer of interconnections formed on the structureof FIG. 7 by the following steps. A layer 42 of silicon dioxide issputtered onto the entire surface covering the exposed portion of layers32 and 37, apertures are opened in the layer 42, where interconnectionsare desired with layer 37, through a photoresist by etching inaccordance with well-known practice, and the photoresist mask is thenremoved.

A layer of titanium 46, 300 angstroms thick, a layer of gold 47, 1000angstroms thick, and a layer of titanium 48, 500 angstroms thick, areapplied in a similar manner to that previously described. A second layerinterconnection photoresist mask (not shown) is formed with aperturesabove the apertures formed in layer 42 and in regions where a second setof interconnects between the elements is desired. The portions of layer48, exposed through the aperture are removed by chemical etching with asolution of NH4F4 and H2O2 and connecting leads 49, 0.5 mil or morethick, are plated through the mask apertures onto the exposed portionsof gold layer 47 to form the structure as shown in FIG. 8a. Thephotoresist mask is then removed by a solvent and the portions of layer48 between the leads 49 are then removed by chemical etching with atitanium etch. Portions of gold layer 47 between leads 48 are thenremoved by chemical etching with a gold etch, or by sputter etchingwhich also removes a small amount of the leads 49, and layer 46 is thenremoved by a titanium etch to form the nal structure as shown in FIG.8b.

Any number of layers of interconnections may be built up in theforegoing manner. If the second layer of interconnections is anintermediate layer, the photoresist mask may be used to form a titaniumlayer sputter etch mask over the desired interconnect region asdescribed for the first interconnect layer. The finished assembly mayhave an insulating protective layer of silicon dioxide or epoxy appliedthereto for surface protection. The final and/or any intermediate layerof interconnections may provide the beam leads for interconnection witha printed circuit support illustrated in FIG. 6.

This completes the description of the embodiment of the inventionillustrated herein; however, many modiiications thereof will be apparentto persons skilled in the art without departing from the spirit andscope of this invention. 'For example, other metals and materials can beused for the lead-ins and the barrier layer and other material such asaluminum oxide can be used as a passivation layer for the semiconductor.In addition, the invention can be used to form multilayer leads whichcross one another on the surface of the chip or on which are grownadditional layers for the formation of electric components for a stackedconfiguration. Also, such metal layer can be focused on surface regionsother than on planar regions such as sloping walls of mesa semiconductorregions formed for example in an epitaxial layer by the preferential oranisotropic etching as heretofore described for separation of the chipsfrom the wafer. Accordingly, it is intended that this invention be notlimited by the particular details of the embodiments illustrated thereinexcept as defined by the appended claims.

What is claimed is:

1. A method of selectively removing material from a body comprisingsputter etching a surface of said body 1n an atmosphere having aconstituent which reacts with a subsurface layer adjacent at leastportions of said surface to form a compound which is removed by sputteretching at a substantially lower rate than other material of said body.

2. The method in accordance with Claim 1 wherein said constitutentcomprises oxygen.

3. The method in accordance with Claim 2 wherein said layer comprises ametal which reacts with oxygen.

4. The combination in accordance with Claim 3 wherein said metalcomprises titanium.

5. The combination in accordance with Claim 4 wherein said atmospherecomprises argon.

6. The combination in accordance with Claim 5 wherein said sputteretching is performed in an electric eld.

7. The combination in accordance with Claim 6 wherein said othermaterial comprises gold or platinum.

8. The method of forming an integrated circuit comprising:

forming a plurality of active elements in a body of semiconductormaterial;

forming a plurality of multilayer conductors interconnecting said activeelements, and formed of a plurality of layers of metals deposited overan insulating layer on said body; and

removing portions of said metal layers by sputter etching in anatmosphere having a constituent which reacts with a subsurface layer ofsaid layers to form a compound which sputter etches at a slower ratethan another of said layers.

9. The method in accordance with Claim 8 wherein said semiconductor bodycomprises silicon.

10. The method in accordance with Claim 9 wherein said insulatingsurface comprises a layer of silicon dioxide.

11. The method in accordance with Claim 10 wherein said insulating layercomprises a passivation layer of silicon nitride.

12. The method in accordance with Claim 11 wherein said insulating layerhas apertures formed therein through which said conductors contact saidactive semiconductor elements.

13. The method in accordance with Claim 12 wherein said conductors arebonded to said elements with a bonding layer comprising platinumsilicide.

14. The method in accordance with Claim 13 wherein said multilayer isvapor or sputter deposited.

15. The method in accordance with Claim 14 wherein said multilayercomprises a titanium layer covered with a platinum layer.

16. The method in accordance with Claim 15 wherein said platinum layeris covered with a layer of gold.

17. The method of forming an integrated circuit cornprising:

forming a body of semiconductor material having an epitaXial surfacelayer in the crystallographic plane;

forming active semiconductor elements in said surface layer;

interconnecting said elements with a conductive matrix of a plurality oflayers of metal positioned on an insulating layer on said surface; and

said conductive matrix being formed by coating said insulating layerwith a plurality of said metal layers which contact said activesemiconductor elements through apertures in said insulating layer withthe upper metal layer being thickened in the regions whereinterconnections of said elements are desired and the metal between saidregions being removed by sputter etching in an atmosphere which reactswith the metal of the lower of said metal layers to form a compoundwhich is removed by sputter etching at a lower rate than said upperlayer.

18. The method in accordance with Claim 17 wherein portions of saidthickened metal layer extend beyond the boundary of said surfaces andsaid body of semiconductor material has been separated from other bodiesof semiconductor material by selective etching of said silicon.

19. The method in accordance with Claim 18 wherein said body ispositioned with said active elements adjacent to a supporting substratehaving an insulating surface with conductors positioned thereon inregistry with portions of said thickened metal layer which extend beyondsaid surface.

References Cited UNITED STATES PATENTS 3,479,269 11/ 1969 Byrnes, Jr. etal. 204--298 X 3,689,392 9/1972 Sandera 204--192 3,661,747 5/1972Byrnes, Jr. et al 204-192 JOHN H. MACK, Primary AExaminer D. R.VALENTINE, Assistant Examiner U.S. Cl. X.R.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3.836.446 Dated Sentember 17. 1974 Inventor(5) Karl H. '1 -liefert It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

Claim 4, column 7, line 9, after "The", delete "combination",

and add method Claim 5, column 7, line l1, after "The", delete"combination",

and add method Claim 6, column 7, line 13, after "The", delete"combination" and add method Claim 7, column 7, line 15, after "The"delete "combination" and add method Signed and sealed this 15th day ofapril U75.

t t eS t C FLASHALL DANN RUTH C. -'EASON Co',L ssioner of PatentsAttesting, Officer and Trademarks USCOMM-DC 603764289 a' us. GQVERNMENTPRINUNG OFFICE; |969 o-ass-:JA

